The present invention relates to electronic circuits, and more particularly, to techniques for performing a built-in self-test of a receiver channel having a serializer.
FIG. 1 is a diagram of a prior art dynamic phase alignment (DPA) built-in self-test (BIST) structure, a receiver channel, and a transmitter channel. Built-in self-test (BIST) refers to a circuit design or testing technique within an integrated circuit (IC) that is used to verify the operation of circuit blocks in the same IC. The transmitter channel includes output buffer 102 and serializer 114. The receiver channel includes input buffer 101, multiplexer 103, dynamic phase alignment (DPA) block 104, first-in-first-out (FIFO) buffer 105, multiplexer 106, bit-slip (BSLIP) block 107, and deserializer 108. The DPA BIST structure of FIG. 1 includes test verifier 110, test pattern generator 111, DPA BIST controller 112, and DPA BIST interface block 113.
Test pattern generator 111 generates test signals. DPA BIST interface block 113 transmits the test signals in parallel through a 10-bit bus to serializer 114 in the transmitter channel. The parallel test signals are serialized in serializer 114. The serialized test signals are transmitted to DPA block 104 through multiplexer 103, then to FIFO buffer 105, then to bit-slip block 107 through multiplexer 106, and then to deserializer 108 in the receiver channel. Deserializer 108 deserializes the test signals. Test verifier 110 then verifies the deserialized test signals.